Flash memory, especially NAND flash memory, is used in a wide range of electronic products, such as MP3 players, digital camera, flash memory stick, mobile phones, PDA, and so on. NAND flash memory is usually structured with 16 neighboring cells serially connected without any contact area in-between to offer high density. Electron tunneling is used for erase/program, i.e., write, operations for low power consumption. NAND flash memory shows promising performance in write-intensive applications that demand faster writing time.
Conventional flash memory is configured as a data region and a spare region. The data region is for storing data, and is usually divided into data blocks, or simply blocks. The spare region is for storing additional information on the usage of the data region. FIG. 1 shows a schematic view of the configuration of a flash memory. As shown in FIG. 1, the spare region contains information such as logical address and the error correction code (ECC) of each flash memory block.
The flash memory management mechanism usually utilizes a translation table. The translation table records the mapping of a logical block address (LBA) to a physical address. When flash memory is powered on, the flash memory management mechanism includes the reconstruction of the translation table, and the translation table is then used for finding the physical address of the read and erase/program operations. FIG. 2 shows a schematic view of a translation table reconstructed from the information in the spare region of FIG. 1. This management mechanism provides good data access efficiency because the mapping of an LBA to a physical address can be easily found in the translation table.
However, a potential problem may occur if the application repetitively writes (erase/program) into the same logical block. This problem, commonly known as disturbance, is caused by the generation of oxide charges during the erase/program operation in flash memory. As the erase/program operation is accomplished by the tunneling algorithm using high voltage of about 20V, which leads to the degradation of the tunnel oxide quality and a failure if it is repeated without the limit. The limit is commonly referred to as endurance. When the number of erase/program operations exceeds the endurance, the un-updated data will be disturbed, i.e., ruined, and lost. Although not all the applications would exceed the endurance, flash memory designers should always bear in mind the existence of the endurance limit.
Many approaches have been developed to alleviate or postpone the disturbance effect. For example, a wear-leveling algorithm can be used to spread the erase/program operations evenly across all the blocks of the flash memory to avoid some of the blocks prematurely reaching the endurance. FIG. 3 shows a schematic view of a wear-leveling algorithm which is applied in the erase/program operation. As shown in FIG. 3, when an updated data is written into a block, the content of the block (with the updates) is copied to an empty block, and the original block is marked as erased. In other words, when an erase/program operation is executed, a different block is used to prevent repetitive wearing of the same data block. Therefore, wear-leveling algorithms prolong the life span of the flash memory.
U.S. Patent Application Publication US 2005/0073884 A1 disclosed a flash memory data correction and scrub technique to maintain the data integrity of flash memory that is susceptible to disturbance caused by operations in adjacent regions of the memory. U.S. Patent Application Publication No. US 2005/0055495 A1 disclosed a method for reducing wearing of memory hotspots by rotating the memory blocks on the physical level. However, the extent to which the wear-leveling algorithm can achieve remains the most important criterion.